AT86RF232
? Bit 4:0 - TRX_CMD
A write access to register bits TRX_CMD initiates a radio transceiver state transition.
Table 7-17. TRX_CMD .
Register Bits
Value
Description
TRX_CMD
0x00
0x02
(1)
(2)
NOP
TX_START
0x03
FORCE_TRX_OFF
0x04
(3)
FORCE_PLL_ON
0x06
0x08
0x09
RX_ON
TRX_OFF (CLK Mode)
PLL_ON (TX_ON)
0x16
0x19
(4)
(4)
RX_AACK_ON
TX_ARET_ON
All other values are reserved
Notes: 1.
2.
3.
4.
TRX_CMD = “0” after power on reset (POR).
The frame transmission starts one symbol after TX_START command.
FORCE_PLL_ON is not valid for states P_ON, SLEEP, and RESET, as well as
STATE_TRANSITION_IN_PROGRESS towards these states.
Extended Operating Mode only.
A successful state transition shall be confirmed by reading register bits TRX_STATUS
(register 0x01, TRX_STATUS).
The register bits TRX_CMD are used for Basic and Extended Operating Modes, refer to
Section 7.1 .
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi-purpose register to control various operating
modes and settings of the radio transceiver.
Figure 7-18 . Register TRX_CTRL_1.
Bit
7
6
5
4
0x04
Read/Write
Reset value
Bit
reserved
R/W
0
3
IRQ_2_EXT_EN
R/W
0
2
TX_AUTO_CRC_
ON
R/W
1
1
RX_BL_CTRL
R/W
0
0
TRX_CTRL_1
0x04
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
TRX_CTRL_1
Read/Write
Reset value
R/W
0
R/W
0
R/W
1
R/W
0
65
8321A – MCU Wireless – 10/11
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